USB 2.0 Verification IPs | Aumraj Silicon Engineering

UVM compliant.
Implemented in System Verilog language.
Configurable: Host, Device or Hub along with support for split transfer verification.
Compatible with all previous versions of USB.
Operates at high, full and low speed.
Supports up to 127 devices.
Supports completely configurable bus enumeration with auto detection of device connection and disconnection.
Supports all descriptor types and device requests.
Communicates with the DUT via UTMI interface.
Supports constrained randomization of packets and its various fields as per USB 2.0 protocol.
Supports all USB 2.0 transfer types: Control, Interrupt, Bulk, Isochronous (Asynchronous, Synchronous, Adaptive).
Supports protocol checking including error detection of CRC, SYNC field, EOP, Bit stuffing, PID.
Built in functional coverage analysis and reporting.
Supports standard USB signals.

Configurable number of transactions.
Supports random generation of all transactions including PING and SPLIT transactions.
Supports randomization of payload length, payload data, target endpoint, address, inter packet gap, end-to-end delay.
Supports payload checking for Data received from device. User can program expected data.

USB 2.0