PCIE E

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PCI-Express

Protocol Overview

Our PCI express verification IP provides comprehensive support to verify PCI express core or PCI express based design. A mature VIP solution that lets designers and verification engineers to verify PCI express based products. It features complete set of verification components including BFM, monitor, checker, tests. It contains easy to use verification library that has extensible set of APIs thus provides ease to users to accelerate their verification process with complete set of test suit. Our PCI express 3.0 Verification IP is based on Universal Verification Methodology (UVM).

Set of Basic features

Compliant with PCI express base specification v3.0, v2.1, v1.1.
VIP can be configured as PCI express Root complex and PCI express end point.
Supports x1, x2, x4, x8, x12, x16,x32 lanes.
Supports verification at PIPE, 10b, and serial interface.
Supports 1-bit, 10-bit, 8-bit, 16-bit, 32-bit PIPE interface.
Ability to generate and drive traffic as a Requester.
Responds to transaction as a completer
Contains wide variety of BFM support through APIs.
Transaction logging and LTSSM support.
Provides directed & constrained random traffic generation.
Complete set of test suits including basic tests, directed tests, random tests, protocol tests, error tests.
Monitor for debugging scenarios, functional coverage.
Checker for protocol checking, real time reporting of violations.
Supports handling of traffic at Transaction, Data Link, and Physical layer.
Supports Generation of flow control packets.
Supports PCI Express credit management.
Supports Read and write transactions to memory, IO, and configuration space.
Supports Message transfer.
Supports Error Injection at all layers either directed way or randomly.

PCIE E

Protocol Overview

Set of Basic features

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