A universal asynchronous receiver/transmitter that translates data between parallel and serial forms and used for serial communications over a computer or peripheral device serial port.Our UART Verification IP verify UART component of SOC by smarter way and compliant with standard UART 16550 Specification.
UART VIP is supported in SystemVerilog, VMM.

The VMM based UART VIP is suitable for verification of UART Transmitter/Receiver/ Transceiver/Full-Modem/DCE/DTE (Data Terminal Equipment) DUTs and for coverage measurement. VIP can be easily configured and integrated with environment.
 

Features

 

UART Verification env contains following