The Aumraj I2C Verification IP is a solution for verification of I2C master and slave deviceswhere each verification component developed in SystemVerilog. It provides support for standard, fast, and high speed operations and rich set of configuration parameters to set clock synchronization and generation of the Serial Clock Line (SCL) to meet all clocking requirements, Arbitration and Clock Synchronization, START Byte, Device ID, Bus Clear and Clock Stretching, various error injection and detection, Callback in Master and Slave, timing checks in the Monitor. It also offers an easy use and complete verification solution for SoCs incorporating I2C in either Master or Slave or Master-Slave mode at module, chip and system level as well as I2C is written entirely in SystemVerilog enabling it to run natively in supported simulators for highest performance.Its SystemVerilog architecture includes native support for UVM and built-in functional coverage.